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| EUA4996 2.8-W Stereo Fully Differential Audio Power Amplifier DESCRIPTION The EUA4996 is a stereo fully-differential audio amplifier, capable of delivering 2.8W/channel of continuous output power to a 3 load with 10% THD+N from a 5V power supply. The EUA4996 features independent shutdown control for each channel. The feedback resistors are internal, allowing the gain to be set with only two input resistors per channel. High PSRR and fully differential architecture provide increased immunity to noise and RF rectification, and a fast startup time with minimal pop, making the EUA4996 idea for notebook PC, smart phone applications. FEATURES Output Power - 2.8W/Ch Into 3 at 5V, THD=10% (Typ.) - 1.99W/Ch Into 4 at 5V, THD=1% (Typ.) - 1.27W/Ch Into 8 at 5V, THD=1% (Typ.) Wide Supply Voltage: 2.5V to 5.5V Independent Shutdown Control for Each Channel High PSRR : 86dB Fast 23ms Startup Time with Minimal POP Low 8mA Quiescent Current at 5V Supply and 1A Shutdown Current Thermal Protection 4mm x 4mm TQFN-16 Package RoHS Compliant and 100% Lead(Pb)-Free APPLICATIONS Notebook PCs Smart Phones Typical Application Circuit Figure 1. DS4996 Ver0.1 July 2008 1 EUA4996 Pin Configurations Package Type Pin Configurations TQFN-16 Pin Description PIN ROUT+ GND ROUTLOUT+ LOUTTQFN-16 1 2,5 3 4 6 7 8 9 10 11 12 13 14 15 16 I/O O I DESCRIPTION Right channel positive BTL output High current ground Right channel negative BTL output Left channel positive BTL output Left channel negative BTL output Left channel power supply. Must be tied to RVDD for stereo operation. Left channel shutdown terminal (active low logic) Left channel mid-supply voltage. Adding a bypass capacitor improves PSRR Left channel positive differential input Left channel negative differential input Right channel shutdown terminal (active low logic) Right channel mid-supply voltage. Adding a bypass capacitor improves PSRR Right channel positive differential input Right channel negative differential input Power supply O O O I I I I I I I LVDD LS/D LBYPASS LIN+ LIN- RS/D RBYPASS RIN+ RINRVDD DS4996 Ver0.1 July 2008 2 EUA4996 Ordering Information Order Number EUA4996JIR1 Package Type TQFN-16 Marking xxxxx A4996 Operating Temperature Range -40C to 85C EUA4996 1/4 1/4 1/4 1/4 Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: TQFN DS4996 Ver0.1 July 2008 3 EUA4996 Absolute Maximum Ratings u u u u Supply voltage, VDD -------------------------------------------------------------------------------------------- 6V Input voltage, VI ---------------------------------------------------------------------------- -0.3 V to VDD +0.3V Storage temperature rang, Tstg ------------------------------------------------------------------- -65C to 150C Junction Temperature -------------------------------------------------------------------------------------- 150C Recommended Operating Conditions Supply Voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Operating free-air temperature, TA MIN NOM MAX UNIT 2.5 5.5 V 1.55 V 0.5 -40 85 C Electrical Characteristics, TA=25C Symbol VOS Parameter Output offset voltage (measured differentially) Conditions VI=0V differential, Gain=1V/V, VDD=5.5V VDD=2.5V to 5.5V VDD=2.5V to 5.5V VDD=2.5V, VIC=0.5V to 1.7V VDD=5.5V, VIC=0.5V to 4.7V RL=3, Gain=1V/V VDD=5.5V VIN+=VDD, VIN-=0V or VDD=3.6V VIN+=0V, VIN-=VDD VDD=2.5V RL=3, Gain=1V/V VDD=5.5V VIN+=VDD, VIN-=0V or VDD=3.6V VIN-=VDD, VIN+=0V VDD=2.5V VDD=5.5V, VDD=5.5V, VI=5.8V VI=-0.3V EUA4996 Unit Min Typ Max. -9 0.8 -87 0.5 -63 -63 0.55 0.42 0.34 4.9 3.1 2.1 58 3 8 0.08 38k RI 40k RI 100 1 42k RI VDD-0.8 9 mV dB V dB PSRR Power supply rejection ratio VIC CMRR Common mode input range Common mode rejection range Low-output swing V 0.4 V 100 100 A A mA A V/V k High-output swing |IIH| |IIL| IQ I(SD) High-level input current, Shutdown 1.9 Low-level input current, Shutdown Quiescent current Supply current Gain Resistance from shutdown to GND VDD=2.5V to 5.5V, with load V( Shutdown )0.5V, VDD=2.5V to 5.5V, RL= 3 RL= 3 DS4996 Ver0.1 July 2008 4 EUA4996 Operating Characteristics, TA=25C, Gain=1V/V EUA4996 Symbol Parameter Conditions VDD=5V VDD=3.6V VDD=2.5V VDD=5V VDD=3.6V VDD=2.5V VDD=5V VDD=3.6V VDD=2.5V PO=2W f=1kHz ,RL=3 PO=1W PO=300mW Total harmonic distortion THD+N plus noise PO=1.8W f=1kHz ,RL=4 PO=0.7W PO=300mW PO=1W f=1kHz ,RL=8 PO=0.5W PO=200mW KSVR Supply ripple rejection ratio Crosstalk SNR Vn Signal-to-noise ratio Output voltage noise Common mode rejection ratio Input impedance VDD=5V VDD=3.6V VDD=2.5V VDD=5V VDD=3.6V VDD=2.5V VDD=5V VDD=3.6V VDD=2.5V Min Typ 2.25 1.13 0.46 1.99 1 0.42 1.27 0.65 0.29 0.16 0.19 0.08 0.09 0.06 0.07 0.04 0.04 0.05 -86 -80 -99 106 12 8.7 -60 Max. Unit THD+N=1%, f=1kHz,RL=3 PO Output power THD+N=1%, f=1kHz,RL=4 W THD+N=1%, f=1kHz,RL=8 % VDD=3.6V, f = 217Hz Inputs ac-grounded with Ci=2F, f = 1kHz V(Ripple)=200mVpp VDD=5V, RL=3, f=1kHz ,PO=1W VDD=5V, PO=2W,RL=3,f=1kHz,Gain=1V/V No VDD=3.6V, f=20Hz to 20kHz, weighting Gain=1V/V ,Inputs ac-grounded A with CI=0.22F weighting VDD=3.6V,VIC=200mVPP f=217Hz 38 dB dB dB VRMS CMRR ZI dB 42 k 40 Start-up time from VDD=3.6V, CBYPASS=0.1F 23 ms shutdown Note: The thermal performance of the TQFN package when used with the exposed- DAP connected to a thermal plane is sufficient for driving 4 or 3 loads. DS4996 Ver0.1 July 2008 5 EUA4996 Typical Operating Characteristics Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 DS4996 Ver0.1 July 2008 Figure 7 6 EUA4996 Typical Operating Characteristics (continued) Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 DS4996 Ver0.1 July 2008 Figure 13 7 EUA4996 Typical Operating Characteristics (continued) Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 DS4996 Ver0.1 July 2008 Figure 19 8 EUA4996 Typical Operating Characteristics (continued) Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 DS4996 Ver0.1 July 2008 Figure 25 9 EUA4996 Application Information Fully Differential Amplifier The EUA4996 is a fully differential amplifier that features differential inputs and outputs. The EUA4996 also includes a common mode feedback loop that controls the output bias value to average it at VCC/2 for any DC common mode input voltage. This allows the device to always have a maximum output voltage swing, and by consequence, maximize the output power. Moreover, as the load is connected differentially, compared to a single-ended topology, the output is four times higher for the same power supply voltage. The fully differential EUA4996 can still be used with a single-ended input; however, the EUA4996 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully Differential Amplifiers The advantages of a full-differential amplifier are: Very high PSRR (Power Supply Rejection Ratio). High common mode noise rejection. Virtually zero pop without additional circuitry, giving an faster start-up time compared to conventional single-ended input amplifiers. No input coupling capacitors required thanks to common mode feedback loop. Midsupply bypass capacitor not required. Application Schematics Figure 26 through Figure 27 show application schematics for differential and single-ended inputs. Typical values are shown in Table1. Table1. Typical Component Value Component RI C(BYPASS) CS CI Value 40k 0.22F 1F 0.22F thermal resistance of the application can be reduced, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the EUA4996. If TJMAX still exceeds 150C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Figure 26.Differential Input Application Schematic Optimized with Input Capacitors Power Dissipation Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. The maximum power dissipation for a given application can be derived from the power dissipation graphs of from equation1. P DMAX = 4 * (VDD ) 2 /(2 2 R L ) ------------(1) It is critical that the maximum junction temperature TJMAX of 150C is not exceeded. TJMAX can be determine from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the DS4996 Ver0.1 July 2008 Figure 27.Single-Ended Input Application Schematic 10 EUA4996 Proper Selection of External Components Gain-Setting Resistor Selection The input resistor (RI) can be selected to set the gain of the amplifier according to equation2. Gain=RF/RI (2) The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10k and the specification calls for a flat bass response down to 100Hz. Equation 3 is reconfigured as equation4. 1 C= (4) I 2 R f IC In this example, CI is 0.16F, so one would likely choose a value in the range of 0.22F to 0.47F. Ceramic capacitors should be used when possible, as they are the best choice in preventing leakage current. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. Decoupling Capacitor (CS) The EUA4996 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F to 1 F, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a 10-F or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device. Each VDD pin must have a separate power supply decoupling capacitor. Additionally, the left and high channel VDD pins must be tied together on the PCB. The internal feedback resistors (RF) are trimmed to 40k. Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Bypass Capacitors (CBYPASS) and Start-up Time The internal voltage divider at the Bypass pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin and increases kSVR. C(BYPASS) also determines the rise time of VO+ and VO- when the device is taken out of shutdown. The larger the capacitor, the slower the rise time. IF Bypass Capacitors are used, it is necessary to use separate bypass capacitors for each bypass pin. Input Capacitor (CI) The EUA4996 does not require input coupling capacitors if using a differential input source that is biased from 0.5V to VDD -0.8V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency determined in equation3. 1 f= (3) C 2 R C II DS4996 Ver0.1 July 2008 11 EUA4996 Package Information TQFN-16 DETAILA SYMBOLS A A1 b E D D1 E1 e L MILLIMETERS MIN. MAX. 0.70 0.80 0.00 0.05 0.25 0.35 3.90 4.10 3.90 4.10 2.50 2.50 0.65 0.30 0.50 INCHES MIN. 0.028 0.000 0.009 0.153 0.153 0.098 0.098 0.026 0.012 0.020 MAX. 0.031 0.002 0.014 0.161 0.161 DS4996 Ver0.1 July 2008 12 |
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